Corto123 发表于 2020-2-29 18:09
Hello all,
I succeeded to implement a software workaround concerning the "trigger issue".
With this ...
What's the nature of workaround? To me it looked mostly like a race condition, and a lack of proper synchronization between cpu and fpga. I gave it up trying to make those run along smoothly.
Corto123 发表于 2020-2-29 18:09
Hello all,
I succeeded to implement a software workaround concerning the "trigger issue".
With this ...
Definitely helped with Single trigger mode, but it still erratic in Auto mode.
Connecting channel A to inbuilt signal generator, it stops updating the screen above 20mS/div
The strange display you observed is, in my opinion, due to the exact synchronization between the FPGA and the CPU.
The CPU generates the FPGA clock (1Mhz x 10) and the sampling rate is the exact multiple of the output frequency.
So each sample can correspond to the same position on the signal shape.
However the auto mode has to be fixed. I work on a correction.
I tried A and B versions and both works fine for me in auto,norm and single mode, B version just reload signal curve with less time than A, trigger in single mode from left side of table(see trigger mode chart) is gone, that is good job, maybe this two apps works fine because I have fpga from 1.20.
发表于 2020-3-1 05:15:10
