The FPGA provides an API that is quite simple, but it returns un consistent status in the following phases:
1/ At the FPGA init phase after a powered ON.
2/ At the moment the signal(s) sampling is started.
3/ During the pre-sampling phase (wait for trigger) under certain conditions (i.e. single mode started in high sampling frequency)..
My work was to try to determine exactly in which conditions these wrong status are returned (quite difficult!).
Happily, the problem is always related to the FPGA init phase: there is no problem later.
The solution I found is to restart the FPGA as soon as any un consistent status is detected, during these critical phases.
This workaround doesn't consume CPU load and doesn't affect the real time performances of the DSO.

This is my e-mail adress: philippe.lafargue@free.fr